AMD Job - 39828055 | CareerArc
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Company: AMD
Location: Santa Clara, CA
Career Level: Mid-Senior Level
Industries: Technology, Software, IT, Electronics

Description


What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

Sr Silicon Design Engineer

THE ROLE:

Be a member of the team that plays a meaningful role in ensuring the quality of next generation microprocessors through structured DFT, Automatic Test Pattern Generation (ATPG). Collaborate with other DFT engineers, RTL owners, circuit designers and physical designers on design solutions that improve test and fault coverage while ensuring successful implementation of the design under the pre-set specifications.

 

THIS PERSON:

We are looking for someone with experience in Scan ATPG/DFT and will be responsible for supporting the Scan DFT functions of mixed signal IPs throughout the design process. Will also have strong communication; debug skills & possess the ability to work across function and with co-workers around the globe.

 

KNOWLEDGE & KEY RESPONSIBILITES:

  • Experience with Automated Test Pattern Generation - ATPG / ScanDFT. Mentor Graphics Tessent Scan (FastScan/TestKompress) and/or Synopsys TetraMAX or Cadence Modus (EncounterTest).
  • Knowledge of Verilog and System Verilog
  • Experience with Simulation Debug (VCS/Verdi)
  • Silicon Debug / Yield Analysis
  • Knowledge of IEEE 1149.* Standards (JTAG/Boundary Scan) & IEEE 1500 standard.

 

PREFERRED EXPERIENCE:

  • Additional experience with Tetramax and/or Modus is a plus!
  • Any analog/mixed-signal DFT experience
  • DFT Compiler / Design Compiler

 

ACADEMIC CREDENTIALS:

  • Master's degree in Electrical/Computer Engineering and/or 2-3 years of applicable scan ATPG experience

 

LOCATION:

  • Ft Collins, Colorado

 

Pay Range:

  • Expected to range from $80,000 to $115,000, commensurate with experience and specific skill sets.  This role also provides a competitive bonus and benefits package.

#LI-ZL2

 



Requisition Number: 99264 
Country: United States State: California City: Santa Clara 
Job Function: Design  

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.


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