SMTS Silicon Design Engineer Job Listing at AMD in Vancouver, BC (Job ID 35734-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

SMTS SILICON DESIGN ENGINEER

THE TEAM:

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. 

AMD together we advance_

G&E MI SOC DFx team is responsible for architecting, integrating, verifying, performing timing analysis of DFx (Design-For-Test & Design-For-Debug) logic in state-of-the-art artificial intelligence and machine learning accelerator products for data-centers. The team is also responsible for generation, validation, delivery, and silicon bring-up of all structural test content for production testing of the complex 3D stacked-die SoC products developed using most advanced technology nodes. We are working with Software Debug Tools and Platform debug teams to enable debug solutions for full platforms. Out team architected and implemented DFx solution for AMD Instinct™ MI300 Series Accelerators. We are constantly working on improving DFx architecture and methodology, developing new features and flows. Our team have very tight interaction with other SoC functions, such as Physical design, Functional Verification, IP Integration, Package design as well as with IP Design, Debug SW tools, Product Engineering, Platform Debug teams.

THE ROLE:

We are currently looking for a SOC DFx Technical staff engineer (MTS, SMTS or PMTS level) who will be part of a team working on next generation of a complex multi-chiplet MI accelerator SOC design.

The successful candidate will have the opportunity to be involved in all stages of the project execution, from high level definition of the design, test plan reviews, through design, verification and emulation of those features until deliveries of the test vectors to product engineering, and silicon bring-up. You will technically lead a team of several engineers working on DFT Design verification and/or Scan Insertion and ATPG. You can also be working on Architecture and Methodology improvements in different areas of DFT.

THE PERSON:

You have strong hand-on technical experience in different DFx areas, a team player who has excellent communication skills, good at leading, guiding and mentoring junior engineers. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems, able to work well in a dynamic, fast-paced environment. Welcome to the team!

KEY RESPONSIBILITIES:

• Technically lead a team of engineers responsible for DFx design verification and/or Scan-Insertion and ATPG.
• Perform Scan-Insertion, DRC, ATPG, pattern retargeting, pattern simulations.
• Drive structural test coverage improvement.
• Participate in verification test-plan development and reviews.
• Write tests, sequences, and testbench components in C++
• Drive verification coverage improvement.
• Participate in develop and improving DFT architecture solutions, flows and methodologies.

PREFERRED EXPERIENCE:

• 7+ years of ASIC design experience
• Hands-on working experience in DFT design and flows such as Scan Insertion, ATPG, Memory-BIST insertion.
• Understanding and experience with DFT structures and methods such as - iJTAG, Scan, ATPG, EDT Scan compression, SSN, at-speed testing using PLL, Memory BIST and repair, Logic BIST, on-chip debug logic.
• Experience in VCS RTL and Gate-level simulations. Experience with design emulation is a plus.
• Hands-on Experience with Scripting languages (e.g. Perl, TCL, Ruby, Shell scripting), and C++.
• Familiar with entire ASIC architecture and design flow.
• Hands-on experience in logical design and design verification.
• Experience in test patterns generation and silicon bring-up on ATE and in the lab.  
• Understanding Analog and Mixed-signal logic design and testing is a plus.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in Electrical Engineering, Computer Science, or Computer Engineering

LOCATION:

Vancouver or Markham

#LI-Hybrid

#LI-PU1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.