SMTS Silicon Design Engineer Job Listing at AMD in Shanghai (Job ID 40925-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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IP Firmware Architect

THE ROLE:

The role will work in an IP team as a senior engineer individual contributor or as a technical leader, who will work with IP Arch/designer/other DV to define, implement and verify IP fw sequence. The role also need to work cross IP/soc team for communication, alignment and co-work to deliver successful productions to customers.

THE PERSON:

The candidate is preferred to be PhD with minimum of 8 years, MSEE with minimum of 10 years, or BSEE with minimum of 12 years experience in digital ASIC design/verification/validation or FW domain, with FW/SW/HW cooperation experience. 

KEY RESPONSIBILITIES:

• The successful candidate will act as IP FW architect, be responsible to align for IP fw programming guide with HW/FW team, do fw demo code writing and simulation in pre-silicon.  Join emulation and post silicon debug to tune IP fw sequence.
• PMTS candidate should be able to work independently on new domain and deploy new methodology to wider range, driving a system task cross teams.

PREFERRED EXPERIENCE:

• Digital IP design/verification/validation or fw/hw co-simulation experience.
• Good understanding of hw/sw/fw cooperation principle.
• Good understanding on x86 system work mechanism, understand fw/sw general rule.
• Good experience on fw writing and debug experience or experience to co-work with f/w team for fw sequence define in embedded design.
• Innovation for quality/efficiency improvement.
• Good documentation.
• Good logical thinking and expression. Can describe a technical issue/topic to audience not familiar with it.
• Good cooperation and influence cross teams.
• It's a plus if have one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, PCIe protocol.
• It's a plus to be good at post silicon debug, emulation validation.

ACADEMIC CREDENTIALS:

• The candidate is preferred to be PhD with minimum of 8 years, MSEE with minimum of 10 years, or BSEE with minimum of 12 years experience in digital ASIC design/verification/validation or FW domain, with good FW/SW/HW cooperation experience. 

LOCATION:

Shanghai,Beijing

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.