Description
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
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SMTS SILICON DESIGN ENGINEER
THE ROLE:
CIT (Chiplet Interconnect Technology) team delivers industry leading high-performance interconnects IP for all AMD products including Server, GPU, Client and Game consoles. CIT includes AMD Internal links as well as Industry Standard links for on-chip connections.
We are searching for a designer to join the fast-growing CIT team, and be responsible for defining, specifying, and implementing current and future high-speed I/O IPs. The candidate will be involved in digital design and will be to work on the micro-architecture of leading IPs.
THE PERSON:
People who have the passion to work on leading edge technology, who have solid design capability and communication skills will be successful in this role.
Strong team spirit
Drive to completion
Fluent verbal English
KEY RESPONSIBILITIES:
Defining and implementing the RTL of a new AMD chiplet interconnect IP
Participate in RTL implementation for functional blocks of the IP
Optimize RTL implementation from implementation perspective in cooperation with RTL and Architecture teams
Optimization of physical implementation in cooperation with Physical Design team.
Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)
PREFERRED EXPERIENCE:
Experience in digital front-end implementation, including micro-arch. definition
Experience with state-of-the-art industry standard digital tools
RTL design experience with multi-clock, high frequency designs
Knowledge in digital RTL Design and Implementation
Basic understanding in high-speed I/O protocols (PCIe, UCIe…)
ACADEMIC CREDENTIALS:
Candidate is preferred to be MSEE or BSEE with 10+ years experience in digital ASIC design.
LOCATION:
Shanghai
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
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